In this study, the design of a monolithic wideband low-noise amplifier (LNA) is presented and addressed with circuitry and modelling techniques which make it suitable for system integration. Particular emphasis has been dedicated to the interconnections analysis and to the enforcement of the stability characteristics that is usually a crucial point for LNAs. The proposed monolithic microwave integrated circuit (MMIC) amplifier covers the Q/V band showing valuable linear and non-linear characteristics in the full bandwidth from 40 to 51 GHz. The amplifier has been realised with the new 0.1 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process provided by UMS Foundry, and it is suitable for radar and space applications. The LNA shows a noise figure <2 dB, a gain of 16 dB with a 1 dB compression point of 5 dBm. The amplifier is matched at both input and output ports, and also the bond wires are taken into account in the design. The integrability characteristics have been validated with measurements in a dedicated Test-Jig.

Analysis and design of a Q/V-band low-noise amplifier in GaAs-based 0.1 μm pHEMT technology

PANTOLI, LEONARDO;LEUZZI, GIORGIO;
2016

Abstract

In this study, the design of a monolithic wideband low-noise amplifier (LNA) is presented and addressed with circuitry and modelling techniques which make it suitable for system integration. Particular emphasis has been dedicated to the interconnections analysis and to the enforcement of the stability characteristics that is usually a crucial point for LNAs. The proposed monolithic microwave integrated circuit (MMIC) amplifier covers the Q/V band showing valuable linear and non-linear characteristics in the full bandwidth from 40 to 51 GHz. The amplifier has been realised with the new 0.1 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process provided by UMS Foundry, and it is suitable for radar and space applications. The LNA shows a noise figure <2 dB, a gain of 16 dB with a 1 dB compression point of 5 dBm. The amplifier is matched at both input and output ports, and also the bond wires are taken into account in the design. The integrability characteristics have been validated with measurements in a dedicated Test-Jig.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/110773
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