An analytical method for performance evaluation of digital transparent satellite processors

Current perspectives for satellite communications are massively envisaging the introduction of a new generation of satellites based on semi-transparent transponder architectures. In this frame, technological constraints related to the development and implementation of novel payloads, that include significant on-board digital processing, call for careful system modeling and accurate digital hardware design in order to enable feasible trade-offs between hardware efficiency and overall link-budget performance. In this perspective, the present paper proposes a system model and a theoretical framework that include the following steps: i) fine characterization of the causes of non ideal behavior in all stages of a digital on-board processor, with definition of equivalent noise sources for the various blocks and derivation of their parameters, namely the noise figure and the noise temperature; ii) extension of the typical link-budget approach to incorporate contributions of the on-board digital segments. Numerical results are provided to validate the accuracy of approximations introduced in analytical modeling of the various blocks; a comparison with results obtained through C based Monte Carlo simulation is provided. Then a set of results are reported to illustrate - in a real satellite link design example - how the model can support advanced trade-offs that are of primary interest in the design of next generation satellite transponders, e,g. those based on translucent processors (digital transparent).