Latest developments in satellite communications encompass semi-transparent transponder architectures. Such architectures have potentials i) to operate with enhanced frequency planning flexibility and physical layer specifications of evolving communications standards, and ii) to support dynamic reconfiguration of connectivity plans. In this frame, significant on-board digital processing is involved, which calls for careful system modelling and accurate digital hardware design to achieve feasible trade-offs between hardware efficiency and overall link-budget performance. In our recent works we have proposed and validated a quantitative framework for performance analysis and design of Digital Transparent Processors (DTP): the model relies on an extended notion of noise figure that allows a radio link-budget to natively incorporate the non-ideal behaviour (e.g. quantization and rounding errors, linear distortions) of the various DTP segments. The present paperPart of this paper has been presented at IEEE ICC’2017complements the work presented in SGSFIEEEGLOBECOM2016,SGSFsubmittedtoTransaction by providing i) an explicit computation of implementation complexity of a DTP, and ii) a methodology to carry out a complete design flow that moves from system requirements and brings to a detailed definition of digital HW components in the DTP. Through numerical examples we demonstrate that, given a requirement on the overall link budget performance in contexts of practical interest, significant differences in HW complexity are obtained for different design choices.

Design of Digital Satellite Processors: from Communications Link Performance to Hardware Complexity

Sulli, V.
;
Santucci, F.;Faccio, M.;Marini, G.
2018-01-01

Abstract

Latest developments in satellite communications encompass semi-transparent transponder architectures. Such architectures have potentials i) to operate with enhanced frequency planning flexibility and physical layer specifications of evolving communications standards, and ii) to support dynamic reconfiguration of connectivity plans. In this frame, significant on-board digital processing is involved, which calls for careful system modelling and accurate digital hardware design to achieve feasible trade-offs between hardware efficiency and overall link-budget performance. In our recent works we have proposed and validated a quantitative framework for performance analysis and design of Digital Transparent Processors (DTP): the model relies on an extended notion of noise figure that allows a radio link-budget to natively incorporate the non-ideal behaviour (e.g. quantization and rounding errors, linear distortions) of the various DTP segments. The present paperPart of this paper has been presented at IEEE ICC’2017complements the work presented in SGSFIEEEGLOBECOM2016,SGSFsubmittedtoTransaction by providing i) an explicit computation of implementation complexity of a DTP, and ii) a methodology to carry out a complete design flow that moves from system requirements and brings to a detailed definition of digital HW components in the DTP. Through numerical examples we demonstrate that, given a requirement on the overall link budget performance in contexts of practical interest, significant differences in HW complexity are obtained for different design choices.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/122648
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