Computing the hardware complexity of digital transparent satellite processors on the basis of performance requirements

Latest developments in satellite communications encompass semi-transparent transponder architectures. Such architectures have potentials i) to operate with enhanced frequency planning flexibility and physical layer specifications of evolving communications standards, and ii) to support dynamic reconfiguration of connectivity plans, especially desirable in packet switching transport modes. In this frame, significant on-board digital processing is involved, which calls for careful system modelling and accurate digital hardware design to achieve feasible trade-offs between hardware efficiency and overall linkbudget performance. In a companion paper [1] we have proposed and validated a quantitative framework for performance analysis and design of Digital Transparent Processors (DTP): the model relies on an extended notion of noise figure that allows a radio link-budget to natively incorporate the non-ideal behaviour (e.g. quantization and rounding errors, linear distortions) of the various DTP segments. The present paper complements the work presented in [1] by providing i) an explicit computation of implementation complexity of a DTP, and ii) a methodology to carry out a complete design flow that moves from system requirements and brings to a detailed definition of digital HW components in the DTP. Examples are provided in contexts of practical interest.