In this study, the authors present the design and measurement results of a voltage-controlled oscillator (VCO) that is based on a Colpitts core topology and a cascade output buffer. The circuit has a centre frequency of 176 GHz and is implemented in a 130 nm SiGe BiCMOS technology provided by IHP foundry. The VCO is a differential fundamental wave tunable oscillator that makes use of a transistor-based LC-resonator. On-wafer measurements show a tuning range of about 5% from 171 to 179.5 GHz. The circuit achieves a maximum output power of 7.3 dBm when biased at 1.6 V and 6.5 dBm if biased at 1.4 V, both with an efficiency of 6.6%. DC power consumption is 82 and 52 mW, respectively. The measured phase-noise of the VCO is − 110 dBc/Hz at 10 MHz offset. The VCO demonstrates state-of-the-art performance at these frequencies with very good performance in term of output power, efficiency linearity, phase noise and compactness; in addition, thanks to the proposed architecture it shows high integrability at the system level.

Low phase-noise high output power 176-GHz voltage-controlled oscillator in a 130-nm BiCMOS technology

BELLO, HABEEB;Pantoli L.;Leuzzi G.
2019-01-01

Abstract

In this study, the authors present the design and measurement results of a voltage-controlled oscillator (VCO) that is based on a Colpitts core topology and a cascade output buffer. The circuit has a centre frequency of 176 GHz and is implemented in a 130 nm SiGe BiCMOS technology provided by IHP foundry. The VCO is a differential fundamental wave tunable oscillator that makes use of a transistor-based LC-resonator. On-wafer measurements show a tuning range of about 5% from 171 to 179.5 GHz. The circuit achieves a maximum output power of 7.3 dBm when biased at 1.6 V and 6.5 dBm if biased at 1.4 V, both with an efficiency of 6.6%. DC power consumption is 82 and 52 mW, respectively. The measured phase-noise of the VCO is − 110 dBc/Hz at 10 MHz offset. The VCO demonstrates state-of-the-art performance at these frequencies with very good performance in term of output power, efficiency linearity, phase noise and compactness; in addition, thanks to the proposed architecture it shows high integrability at the system level.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/142033
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