A new developed cascaded multilevel inverter topology to reduce number of used devices

In this paper, a new developed cascaded multilevel inverter is proposed which has ability of generating a specified number of voltage levels with a reduced number of required IGBTs and DC voltage sources. To produce all even and odd voltage levels, three patterns are proposed which the magnitudes of DC voltage sources are determined based on them. After that the best proposed pattern is compared with some of presented topologies from different aspects, in order to verify the claim of reduction of used devices and find out the merits and demerits of the proposed topology. At the end of this paper, the simulation results by PSCAD/EMTDC software are demonstrated in order to validate the correct operation of the proposed topology.