In this work we present a fully-analogue Duty-Cycle Corrector (DCC) based on a closed-loop circuit topology operating a continuous-time 50% duty-cycle regulation of the generated output clock signal. In particular, a suitable feedback sub-system detects the duty-cycle values of the input and output clock signals and provides a corresponding control voltage. The latter is employed to generate and regulate two levels of currents that properly charge and discharge (asymmetrically) a load capacitor so suitably adjusting the duty-cycle of the output clock signal. The proposed DCC circuit solution, suitable for integrated digital systems, has been designed in AMS 0.35μm standard CMOS integrated technology, powered at 3.3V single supply voltage with a power consumption of about 3.5mW/GHz and an estimated silicon area of about 0.0027mm2(only 16 transistors, 1 capacitor and few off-chip components). Simulation results have demonstrated the capability of the DCC circuit to correct the input clock signal duty-cycle varying from 30% to 70% providing a 50% duty-cycle output clock signal with an error lower than ±1.5%. Moreover, the developed simple DCC architecture is capable to manage input clock signals with an operating frequency ranging from 200kHz to 2GHz (i.e., 4 frequency decades) resulting suitable to be employed for clock signal compensation in general purpose applications.

A 0.35μm CMOS 200kHz-2GHz Fully-Analogue Closed-Loop Circuit for Continuous-Time Clock Duty-Cycle Correction in Integrated Digital Systems

De Marcellis A.;Faccio M.;Palange E.
2018

Abstract

In this work we present a fully-analogue Duty-Cycle Corrector (DCC) based on a closed-loop circuit topology operating a continuous-time 50% duty-cycle regulation of the generated output clock signal. In particular, a suitable feedback sub-system detects the duty-cycle values of the input and output clock signals and provides a corresponding control voltage. The latter is employed to generate and regulate two levels of currents that properly charge and discharge (asymmetrically) a load capacitor so suitably adjusting the duty-cycle of the output clock signal. The proposed DCC circuit solution, suitable for integrated digital systems, has been designed in AMS 0.35μm standard CMOS integrated technology, powered at 3.3V single supply voltage with a power consumption of about 3.5mW/GHz and an estimated silicon area of about 0.0027mm2(only 16 transistors, 1 capacitor and few off-chip components). Simulation results have demonstrated the capability of the DCC circuit to correct the input clock signal duty-cycle varying from 30% to 70% providing a 50% duty-cycle output clock signal with an error lower than ±1.5%. Moreover, the developed simple DCC architecture is capable to manage input clock signals with an operating frequency ranging from 200kHz to 2GHz (i.e., 4 frequency decades) resulting suitable to be employed for clock signal compensation in general purpose applications.
978-1-5386-4881-0
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/144196
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