This paper reports on a True Random Number Generator (TRNG) that makes use of the period jitter introduced by a Phase Locked Loop (PLL) used as seed of entropy. Generally, implementations of fully-digital TRNGs on a Field Programmable Gate Array (FPGA) employ several ring oscillators implemented by a large number of Look-Up-Tables (LUTs). Differently, in this work we propose a reliable FPGA-based architecture of a TRNG that does not need the use of ring oscillators but employs only on-board primitives. The architecture has been implemented on a Xilinx Ultrascale XCKU040-2FFVA1156E FPGA. In addition, other few basic logic elements are employed only for the initial overall system synchronization and for the post-processing operation. In this way, it is possible to largely reduce the needed number of the Configurable Logic Blocks (CLBs) so limiting the TRNG complexity and its overall power consumption without affecting the resulting throughput. Finally, after the post-processing procedure, a 100Mbps output random bitstream provided by the proposed TRNG, passed all the National Institute of Standards and Technology (NIST) tests as well as the Kolmogorov-Smirnov test so making the presented solution suitable for network security applications.

An FPGA-Based Architecture of True Random Number Generator for Network Security Applications

Di Patrizio Stanchieri G.;De Marcellis A.;Faccio M.;Palange E.
2018

Abstract

This paper reports on a True Random Number Generator (TRNG) that makes use of the period jitter introduced by a Phase Locked Loop (PLL) used as seed of entropy. Generally, implementations of fully-digital TRNGs on a Field Programmable Gate Array (FPGA) employ several ring oscillators implemented by a large number of Look-Up-Tables (LUTs). Differently, in this work we propose a reliable FPGA-based architecture of a TRNG that does not need the use of ring oscillators but employs only on-board primitives. The architecture has been implemented on a Xilinx Ultrascale XCKU040-2FFVA1156E FPGA. In addition, other few basic logic elements are employed only for the initial overall system synchronization and for the post-processing operation. In this way, it is possible to largely reduce the needed number of the Configurable Logic Blocks (CLBs) so limiting the TRNG complexity and its overall power consumption without affecting the resulting throughput. Finally, after the post-processing procedure, a 100Mbps output random bitstream provided by the proposed TRNG, passed all the National Institute of Standards and Technology (NIST) tests as well as the Kolmogorov-Smirnov test so making the presented solution suitable for network security applications.
978-1-5386-4881-0
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11697/144197
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