We start with hardware verified interconnect models based on a 3Gb/s serial link. Stepwise recasting of this single ended link proceeds by peeling off the distortions introduced by lossy dielectric, via stubs, trace and via array cross-talk, and outdated connectors. Equalization schemes (4-tap FFE, 2-stage CTLE, 15-tap DFE) are then applied to demonstrate error-free NRZ signaling at 25Gb/s over the rehabilitated link.
Backplane channel design optimization: Recasting a 3Gb/s link to operate at 25Gb/s and above
De Paulis F.
2012-01-01
Abstract
We start with hardware verified interconnect models based on a 3Gb/s serial link. Stepwise recasting of this single ended link proceeds by peeling off the distortions introduced by lossy dielectric, via stubs, trace and via array cross-talk, and outdated connectors. Equalization schemes (4-tap FFE, 2-stage CTLE, 15-tap DFE) are then applied to demonstrate error-free NRZ signaling at 25Gb/s over the rehabilitated link.File in questo prodotto:
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