In this brief, a new circuit topology to realize an electronically tunable grounded capacitor multiplier with extremely low power consumption and low supply voltage requirement is investigated. The proposed circuit uses an electronically tunable second generation voltage conveyor (VCII) and a single floating capacitor. Owing to the translinear principle, current gain of VCII is varied through a control current and, as a result, the value of simulated capacitor is also varied. Favorably the obtained gain is temperature insensitive. Both of the required supply voltage and control currents are very low because all transistors are biased in subthreshold region: therefore, electronic tunability is achieved while the power consumption is kept at very low value. In addition, the circuit realization is very simple since only twelve transistors are required. Simulation results, performed at schematic level in 0.18 μ m CMOS technology and supply voltage of ±0.3V, are presented. It is shown that a multiplication factor from 1 to 100 is possible while the power consumption varies from 10 nW to 67 nW.

A New Extremely Low Power Temperature Insensitive Electronically Tunable VCII-Based Grounded Capacitance Multiplier

Stornelli V.;Safari L.;Barile G.;Ferri G.
2021

Abstract

In this brief, a new circuit topology to realize an electronically tunable grounded capacitor multiplier with extremely low power consumption and low supply voltage requirement is investigated. The proposed circuit uses an electronically tunable second generation voltage conveyor (VCII) and a single floating capacitor. Owing to the translinear principle, current gain of VCII is varied through a control current and, as a result, the value of simulated capacitor is also varied. Favorably the obtained gain is temperature insensitive. Both of the required supply voltage and control currents are very low because all transistors are biased in subthreshold region: therefore, electronic tunability is achieved while the power consumption is kept at very low value. In addition, the circuit realization is very simple since only twelve transistors are required. Simulation results, performed at schematic level in 0.18 μ m CMOS technology and supply voltage of ±0.3V, are presented. It is shown that a multiplication factor from 1 to 100 is possible while the power consumption varies from 10 nW to 67 nW.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11697/153054
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