The increasing operating frequencies and decreasing IC feature size call for 3-D electromagnetic (EM) methods, such as the Partial Element Equivalent Circuit (PEEC) method, as necessary tools for the analysis and design of high-speed systems. Very large systems of equations are often generated by 3-D EM methods and model order reduction (MOR) techniques are commonly used to reduce such a high model complexity. A typical design process includes optimization and design space exploration, and hence requires multiple simulations for different design parameter values. Traditional MOR techniques perform model reduction only with respect to frequency and such design activities call for parameterized MOR (PMOR) methods that can reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as geometrical layout or substrate characteristics. We present a novel PMOR technique applicable to the PEEC method that provides parametric reduced order models, stable and passive by construction, over a user defined design space. We treat the construction of parametric reduced order models on scattered design space grids. Pertinent numerical examples validate the proposed approach. Copyright (C) 2010 John Wiley & Sons, Ltd.

Passivity-preserving interpolation-based parameterized model order reduction of PEEC models based on scattered grids

ANTONINI, GIULIO;
2011

Abstract

The increasing operating frequencies and decreasing IC feature size call for 3-D electromagnetic (EM) methods, such as the Partial Element Equivalent Circuit (PEEC) method, as necessary tools for the analysis and design of high-speed systems. Very large systems of equations are often generated by 3-D EM methods and model order reduction (MOR) techniques are commonly used to reduce such a high model complexity. A typical design process includes optimization and design space exploration, and hence requires multiple simulations for different design parameter values. Traditional MOR techniques perform model reduction only with respect to frequency and such design activities call for parameterized MOR (PMOR) methods that can reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as geometrical layout or substrate characteristics. We present a novel PMOR technique applicable to the PEEC method that provides parametric reduced order models, stable and passive by construction, over a user defined design space. We treat the construction of parametric reduced order models on scattered design space grids. Pertinent numerical examples validate the proposed approach. Copyright (C) 2010 John Wiley & Sons, Ltd.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11697/15379
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