PEEC capacitance extraction of 3-D interconnects

As feature size of electronic devices decreases, fast and accurate capacitance extraction has become increasingly critical for verification and analysis as regard as electromagnetic compatibility and signal integrity issues. The partial element equivalent circuit method is implemented for three-dimensional capacitance extraction of interconnects and very large-scale integration circuits with multiple dielectrics. The electric field coupling due to free and bound charges are analysed and modelled separately thus allowing to distinguish their contribution. The proposed approach provides physical insight, totally compatible fast methods for accelerating matrix-vector products, allows an easy treatment of lossy and dispersive dielectrics and is well suited for applying model order reduction techniques.