Multilevel converters prove to be well-suitable for high and medium voltage systems due to their lower cost and high-redundance design. For STATCOM, Single-star Bridge-cell (SSBC) topology is well applied for its satisfactory performance and superior component count. However, when number of levels increases, more switches are required to be parallelly controlled. Therefore, software-based microcontrollers (e.g. DSPs) shows limitations in terms of I/O built-in pins as well as performance. Alternatively, field programmable gate arrays (FPGAs), with their parallelism capability, are suitable for implementing control of SSBC-STATCOM. Multilevel SSBC-STATCOM control is composed of three layers which are output voltage control layer, internal current control layer and capacitor voltage balancing layer. A dq control based on PI regulators are commonly used for its simplicity and ease in implementation. In this work, detailed control design and implementation of SSBC-STATCOM using FPGA is discussed. Cyclone V FPGA with 50 MHz clock was used to implement control blocks and a hardware set-up of 142 V SSBC-STATCOM was designed to verify the results.

On Control Design and Implementation of Multilevel SSBC STATCOM Using FPGA

Ahmed Majed Saif
;
Carlo Cecati;Concettina Buccella
2019

Abstract

Multilevel converters prove to be well-suitable for high and medium voltage systems due to their lower cost and high-redundance design. For STATCOM, Single-star Bridge-cell (SSBC) topology is well applied for its satisfactory performance and superior component count. However, when number of levels increases, more switches are required to be parallelly controlled. Therefore, software-based microcontrollers (e.g. DSPs) shows limitations in terms of I/O built-in pins as well as performance. Alternatively, field programmable gate arrays (FPGAs), with their parallelism capability, are suitable for implementing control of SSBC-STATCOM. Multilevel SSBC-STATCOM control is composed of three layers which are output voltage control layer, internal current control layer and capacitor voltage balancing layer. A dq control based on PI regulators are commonly used for its simplicity and ease in implementation. In this work, detailed control design and implementation of SSBC-STATCOM using FPGA is discussed. Cyclone V FPGA with 50 MHz clock was used to implement control blocks and a hardware set-up of 142 V SSBC-STATCOM was designed to verify the results.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/161162
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