In this paper, a new topology for asymmetrical cascaded multilevel inverter is proposed. The proposed topology consists of series connection of several basic units. Reduction of number of power switches, driver circuits, IGBTs and dc voltage sources are some advantages of the proposed topology in comparison with the conventional cascaded multilevel inverters. In order to generate all output voltage levels, a new algorithm to determine the magnitudes of dc voltage sources is proposed. Finally, to verify the performance of the proposed inverter, the simulation results by using PSCAD/EMTDC software on a 33-level single-phase inverter are used.

A new basic unit for cascaded multilevel inverters with reduced number of power electronic devices

Babaei E.;Cecati C.
2016

Abstract

In this paper, a new topology for asymmetrical cascaded multilevel inverter is proposed. The proposed topology consists of series connection of several basic units. Reduction of number of power switches, driver circuits, IGBTs and dc voltage sources are some advantages of the proposed topology in comparison with the conventional cascaded multilevel inverters. In order to generate all output voltage levels, a new algorithm to determine the magnitudes of dc voltage sources is proposed. Finally, to verify the performance of the proposed inverter, the simulation results by using PSCAD/EMTDC software on a 33-level single-phase inverter are used.
978-1-5090-0375-4
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11697/161193
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