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EnglishRecently, second generation voltage conveyor (VCII)-based transimpedance amplifiers (TIAs) have begun to find their way in different applications, among which, silicon photomultipliers (SiPMs) interfacing circuitry. There are many advantages which make VCII-based TIAs attractive over conventional circuits: the intrinsic low impedance at VCII current input Y port is very helpful to mitigate the effect of high value sensor capacitance and provides fast response time; the achieved bandwidth is high and due to current mode operation; the circuits enjoy the low-voltage low-power features. As signal-to-noise ratio is a crucial parameter in SiPMs interface circuit applications, here we consider the noise specifications and optimization of VCII-based SiPM interface circuits. The noise model of VCII is introduced and equivalent noise of a VCII-based interface circuit is derived. Methods to optimize trade-offs existing between key parameters including power consumption, gain and noise performance are discussed. Simulation results are also provided showing a considerable reduction of two orders of magnitude in most of the noise performances when compared to the previous work while preserving other performance parameters.
| Titolo: | Noise analysis and optimization of VCII-based SiPM interface circuit |
| Autori: | |
| Data di pubblicazione: | 2020 |
| Rivista: | |
| Handle: | http://hdl.handle.net/11697/161791 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
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http://hdl.handle.net/11697/161791
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