A technique is presented for variability analysis of large circuits described by neutral delayed differential equations. It is based on a delayed formulation of the partial equivalent element method coupled with stochastic collocation schemes. Pertinent numerical results validate the proposed technique.
|Titolo:||Stochastic collocation for uncertainty quantification of systems described by neutral delayed differential equations|
|Data di pubblicazione:||2017|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|