A technique is presented for variability analysis of large circuits described by neutral delayed differential equations. It is based on a delayed formulation of the partial equivalent element method coupled with stochastic collocation schemes. Pertinent numerical results validate the proposed technique.

Stochastic collocation for uncertainty quantification of systems described by neutral delayed differential equations

Romano D.;Antonini G.;
2017

Abstract

A technique is presented for variability analysis of large circuits described by neutral delayed differential equations. It is based on a delayed formulation of the partial equivalent element method coupled with stochastic collocation schemes. Pertinent numerical results validate the proposed technique.
978-0-9960078-3-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/175680
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