The current demand in Power Distribution Network (PDN) design is characterized by the accurate placement of decoupling capacitors and the minimization of their number aimed at cost saving. The paper proposes an optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution. This allows the designer to identify the minimum number of decaps whenever the input impedance satisfies the target impedance requirements. The algorithm is based on the Genetic Algorithm accordingly adapted for the specific application of PDN design. It may involve the evaluation of the input impedance at multiple locations, representing either multiple ICs, as well as multiple power input areas/pins of the same IC. The validation of the developed optimization algorithm is carried out by applying it to a manufactured PCB and by employing typical (low inductance) decaps for PDN design. The optimization process led to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location. An accurate experimental test further validates the optimized PDN.

Genetic Algorithm PDN Optimization based on Minimum Number of Decoupling Capacitors Applied to Arbitrary Target Impedance

De Paulis F.
;
Cecchetti R.;Olivieri C.;
2020

Abstract

The current demand in Power Distribution Network (PDN) design is characterized by the accurate placement of decoupling capacitors and the minimization of their number aimed at cost saving. The paper proposes an optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution. This allows the designer to identify the minimum number of decaps whenever the input impedance satisfies the target impedance requirements. The algorithm is based on the Genetic Algorithm accordingly adapted for the specific application of PDN design. It may involve the evaluation of the input impedance at multiple locations, representing either multiple ICs, as well as multiple power input areas/pins of the same IC. The validation of the developed optimization algorithm is carried out by applying it to a manufactured PCB and by employing typical (low inductance) decaps for PDN design. The optimization process led to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location. An accurate experimental test further validates the optimized PDN.
978-1-7281-7430-3
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11697/182555
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