Feasibility Analysis of Chip-to-Module Channel Operating at 212 Gbps

The ever-growing demand for higher communication data rates calls for better (wider bandwidth) channels, transmitter and receiver noise and equalization. This is exacerbated when the data-rate is expected to double at each iteration of the interface to be standardized, as it is happening for the Ethernet communications. This paper highlights possible strategies for achieving a reliable channel communication at 200 Gbps based on the Chip-to-Module (C2M) interface typically found in data centers. The budgeting among the channel insertion and return losses, number of crosstalk aggressor channels, quality of Tx and Rx ships in terms of noise and advanced equalization schemes will be analyzed. Guidelines for settings the requirements of the channel architecture will be proposed for the channel reliably working at 200 Gbps for the next generation Ethernet communications.