Capacitive multipliers have found wide applications in capacitive interfaces and other analog circuits requiring large value capacitors. Recently a new active building block (ABB) called second generation voltage conveyor (VCII) has been proved to be useful in many analog signal processing applications. Due to the interesting features offered by VCII, in this paper a new VCII based implementation of grounded capacitance multiplier is proposed employing two VCIIs, two resistors and one grounded capacitor. The circuit can produce both positive and negative multiplication factors in a range of -50 to +50. Its main features are wide frequency range, high resolution, low series resistance, simple structure, low power consumption and maximum percentage error of 7.8%. The circuit enjoys high frequency range up to 10 MHz, even if it employs a floating capacitor in its structure. The behavior of the proposed circuit is analysed by taking into account also the effects of VCII parasitic elements and non-ideal gains. SPICE simulation results using a 0.35 mu m CMOS technology parameters are reported. The proposed circuit has been also experimentally tested by using AD844 as VCII. Measurement results on the standalone capacitance multiplier have shown a mean percentage error of 9% across the entire gain range. Finally, the application of the proposed circuit in realizing a low pass filter is also presented to demonstrate the proposed circuit feasibility.

A new VCII based grounded positive/negative capacitance multiplier

Stornelli, V;Safari, L;Barile, G;
2021-01-01

Abstract

Capacitive multipliers have found wide applications in capacitive interfaces and other analog circuits requiring large value capacitors. Recently a new active building block (ABB) called second generation voltage conveyor (VCII) has been proved to be useful in many analog signal processing applications. Due to the interesting features offered by VCII, in this paper a new VCII based implementation of grounded capacitance multiplier is proposed employing two VCIIs, two resistors and one grounded capacitor. The circuit can produce both positive and negative multiplication factors in a range of -50 to +50. Its main features are wide frequency range, high resolution, low series resistance, simple structure, low power consumption and maximum percentage error of 7.8%. The circuit enjoys high frequency range up to 10 MHz, even if it employs a floating capacitor in its structure. The behavior of the proposed circuit is analysed by taking into account also the effects of VCII parasitic elements and non-ideal gains. SPICE simulation results using a 0.35 mu m CMOS technology parameters are reported. The proposed circuit has been also experimentally tested by using AD844 as VCII. Measurement results on the standalone capacitance multiplier have shown a mean percentage error of 9% across the entire gain range. Finally, the application of the proposed circuit in realizing a low pass filter is also presented to demonstrate the proposed circuit feasibility.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/206265
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