In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of three VCIIs and a single grounded capacitor. Using a control current (I-con), the value of impedance at the Y terminal of the VCII is varied, whereby the value of the simulated inductance is tuned. The proposed circuit is designed at a transistor level using 0.18 mu m TSMC CMOS parameters and +/- 0.9 V supply voltage. PSpice simulations are carried out to confirm the effectiveness of the proposed circuit. For a range of Icon from 0 mu A to 50 mu A, the value of the simulated L can be varied from -576 mu H to -324 mu H and from +316 mu H to +576 mu H for negative and positive simulators, respectively, in the frequency range of 100 kHz-3 MHz. Favorably, the value of the series resistance remains below 76 ohm. Simulation results show an error value below 4.8% and power consumption variation is from 1.64 mW to 1.92 mW. Moreover, application of the proposed circuit as a standard band-pass RLC filter is also included.

Realization of an Electronically Tunable Resistor-Less Floating Inductance Simulator Using VCII

Safari, L;Barile, G;Colaiuda, D;Stornelli, V;
2022-01-01

Abstract

In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of three VCIIs and a single grounded capacitor. Using a control current (I-con), the value of impedance at the Y terminal of the VCII is varied, whereby the value of the simulated inductance is tuned. The proposed circuit is designed at a transistor level using 0.18 mu m TSMC CMOS parameters and +/- 0.9 V supply voltage. PSpice simulations are carried out to confirm the effectiveness of the proposed circuit. For a range of Icon from 0 mu A to 50 mu A, the value of the simulated L can be varied from -576 mu H to -324 mu H and from +316 mu H to +576 mu H for negative and positive simulators, respectively, in the frequency range of 100 kHz-3 MHz. Favorably, the value of the series resistance remains below 76 ohm. Simulation results show an error value below 4.8% and power consumption variation is from 1.64 mW to 1.92 mW. Moreover, application of the proposed circuit as a standard band-pass RLC filter is also included.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/206268
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