Early Power Estimation of FPGA-based Digital Transparent Processors for 5G-satcom

As the cost of pure terrestrial coverage will be likely unbearable with increasing capacity needs for rural, remote, and even urban areas, satellite communications are envisaged to play a significant role in the 5G ecosystem in providing ubiquitous coverage, broadcast/multicast services, and an inherent robustness for emergency/disaster recovery. In this perspective both Geosynchronous Orbit and Low Earth Orbit constellations have been considered for development and early stage deployment. When looking at the satellite payload, an appealing solution exploits semi-transparent transponders that rely on Digital Transparent Processors (DTP). These kinds of transponders may provide adequate flexibility with respect to evolving standards and adaptation with respect to time varying traffic patterns. Within a years-long track of research carried out by the authors, the present paper aims at extending the modelling approach already proposed for accurate and costeffective design of DTP by also incorporating dynamic power consumption of hardware architectures. The novel design flow, that spans from link level analysis to the detailed definition of hardware architectures of all sub-systems in the DTP chain, is then presented and validated for some significant setups. Numerical results are then provided and compared with those obtained from a VHDL implementation related to a Xilinx FPGA platform, showing a very promising agreement (in the range of 3-29 percent) for all the blocks composing the DTP chain. This proves the consistence and the relevance of the proposed design approach. In particular, in the perspective of efficient design of payloads for large constellations of small satellites, the proposed approach is ready to enable definition and handling of ambitious optimization frameworks.