CMOS Adaptive Biased Second Generation Voltage Conveyor

In this paper, a new second generation voltage conveyor (VCII) topology with adaptive bias is presented. For the first time, adaptive bias has been exploited in a CMOS VCII circuit, with the goal of reducing power consumption without sacrificing transient performance, in order to design an active building block suitable for very low power sensor interface applications. Dynamic bias is achieved by means of a circuit capable of both detecting the difference between the input voltage at voltage input terminal and the voltage at output terminal, producing an additional bias current proportional to this difference. It is important to note that the same circuit can also sense an increase of the input current at the current-input node, as the current variation produces a voltage change at voltage input terminal. The new topology has been designed in 0.35 μ m AMS technology with a ± 0.9 V supply voltage, and Spice simulations were performed to evaluate performance in terms of slew-rate and power consumption. The same VCII topology, but without dynamic biasing, was also considered for comparison purposes: simulation results showed that the proposed topology is able to guarantee a reduction of more than 2 orders of magnitude in power consumption, with only 3 times worsening of the slew-rate.