Effect of Sampling and Switching Frequencies on the Stability and Grid Current Quality in Grid-Following Inverters

The computation of the control algorithms and the discrete nature of PWM modulation introduce inherent delays in inverters. Typically, the PWM switching frequency is equal to or half of the sampling frequency in grid-following inverters, and limited attention has been given to the feasibility and impact of increasing the switching frequency beyond the sampling frequency. This approach can be advantageous when the sampling frequency is constrained by the microcontroller's execution speed, while the switching frequency remains adjustable based on device capabilities. This paper analyzes the individual effects of computational and PWM delays on the stability of the control loop and the quality of the grid current in grid-following inverters. Simulation studies identify the critical sampling frequency required to maintain stability based on LCL filter parameters. The results demonstrate that, with appropriate filter design and sampling frequency selection, current control stability can be ensured even in very weak grids. Practical considerations for setting the switching frequency above the sampling frequency are outlined, and the impact on grid current quality is evaluated through comparative experimental studies.