Bus-clamping PWM with Common-Mode Voltage Elimination for Dual Six-Phase Inverters with Shared DC-link

This paper proposes a space vector-based pulse width modulation scheme that incorporates common-mode voltage elimination and bus clamping for a dual six-phase inverter configuration driving an asymmetrical six-phase motor with open-end stator windings. The proposed scheme completely eliminates the common-mode voltage generated by both inverters. Additionally, the employed switching sequence enables bus clamping, which reduces switching losses compared to conventional patterns. The clamping strategy also ensures balanced power loss distribution among the switching devices. By eliminating the resultant common-mode voltage, the scheme allows for the use of a shared DC-link between the two inverters. Furthermore, it suppresses non-torque-producing harmonics in the stator windings of the ASPM and achieves higher DC bus utilization compared to conventional six-phase drive configurations. The effectiveness of the proposed scheme is validated through extensive simulations conducted in the MATLAB/Simulink environment.