Optimized DSP-FPGA Communication in CHB-STATCOM with Direct MPC

Digital signal processors (DSPs) and field programmable gate arrays (FPGAs) are extensively used in modular multilevel converters. Integrated analog to digital converters (ADCs) in DSPs implement high-speed samplings of measurements from sensors while FPGAs can handle complex algorithms computations. This work analyzes practical issues arising in DSP to FPGA data communication using serial peripheral interface protocol. A step by step communication strategy to address the delay is presented. The impact on the closed-loop performance is analyzed for a cascaded h-bridge static synchronous compensator controlled by direct model predictive control. Experimental results show that the proposed solution minimizes the communication delay.