A Dual-Ramp Time-To-Digital Conversion Strategy for Event-Driven Photodetection in Mixed-Signal ASICs

This paper presents a mixed-signal dual-ramp Time-to-Digital Converter (TDC) architecture specifically designed for precise time measurement in Silicon Photomultipliers (SiPMs)-based photodetection applications. The proposed system integrates a regulated common-gate transimpedance amplifier, a high-speed comparator, and a hybrid digital control logic to accurately capture the time interval between a global shutter (GS) signal and photon detection. The dual-ramp approach is crucial for enhancing the system's resolution and linearity beyond the intrinsic limit of the clock period. Post-layout simulations have demonstrated a time resolution of 5 ns using a 20 MHz clock and a stretch factor (K) of approximately 10. Over a 370 ns interval, an average error of only 2 ns was recorded, primarily attributed to delays within the front-end electronics. A Monte Carlo analysis conducted on 1000 samples confirmed the robustness of the system against process variations, with ramp slope deviations below 8%. Additionally, PVT (Process, Voltage, Temperature) analysis showed slope variations of less than 7% across process corners, further validating the system's resilience to mismatch and technological variability. These results collectively validate the effectiveness of the proposed TDC architecture, which combines simplicity and precision, making it well-suited for integration into front-end ASICs for time-charge measurement in photon detection and other rare-event applications.