Low Latency Model Predictive Control Design in Multilevel Inverters with SPI and DSP-FPGA

Digital signal processors (DSPs) and field programmable gate arrays (FPGAs) are widely used in MMCs. DSPs embed analog to digital converters (ADCs) to perform high-speed samplings, pulse width modulation modules, and implement communication protocols to transmit data to other modules or the main controller. On the other hand, FPGAs are employed to handle a large number of input and output signals and to provide hardware acceleration for computationally intensive control algorithms. This work analyzes the practical challenges of establishing serial peripheral interface (SPI) communication between an FPGA and a DSP. Starting from a basic implementation scheme, the paper presents four scenarios, addressing issues step-by-step toward the development of an SPI communication with minimum delay. Moreover, the impact of communication delays on a cascaded h-bridge inverter implementing model predictive control (MPC) is investigated. The aim of this paper is twofold. First, it provides practical guidelines for establishing an optimized SPI communication between FPGA and DSP. Second, it analyzes the effect of delays to the output waveforms of an MPC-driven multilevel inverter, evaluating the robustness of the MPC to measurement acquisition delays. This analysis is carried out both analytically and through experimental results on a 5-level cascaded h-bridge prototype.