Buried Capacitance Technology for Power Bus Decoupling on High Speed Digital PCB's

In the modern digital equipments, as the speed of the ASICs and the complexity of the PCBs increase, the electronic designers have to control the noise on the boards to avoid EMC and signal integrity problems. One of the main kinds of noise on the PCBs is the ∆I-noise, which may jeopardize the operation of sensitive integrated circuits. To solve this problem, decoupling power supply techniques, suitable for multilayer PCBs with very large ASIC package sizes, have to be developed. This paper analyzes a power bus decoupling technique using some discrete capacitors with two power/ground planes, adjacent to one another and separated by a thin FR-4 dielectric material, on a 16 layers PCB. On the PCB there is an ASIC with a large package size (EPBGA 596) and output signals with rise/fall times equal to 400ps. The carried out transfer impedance measurements on the ASIC power plane highlight as the above mentioned technique may be useful in the high frequency PCB design process.