Voltage source inverter (VSI) fed six-phase induc- tion motor drives have high 6 n 1 ; n = odd order harmonic currents, due to absence of back emf for these currents. To sup- press these harmonic currents, either bulky inductive harmonic filters or complex pulse width modulation (PWM) techniques have to be used. This paper proposes a simple harmonic elimination scheme using capacitor fed inverters, for an asymmetrical six- phase induction motor VSI fed drive. Two three phase inverters fed from a single capacitor is used on the open-end side of the motor, to suppress 6 n 1 ; n = odd order harmonics. A PWM scheme that can suppress the harmonics, as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected. The proposed scheme is verified using MATLAB Simulink simulation at different speeds. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. Experimental results are also provided to validate the functionality of the proposed controller

A 5th and 7th order harmonic suppression scheme for open-end winding asymmetrical six-phase IM drive using capacitor-fed inverter

CECATI, Carlo
2013-01-01

Abstract

Voltage source inverter (VSI) fed six-phase induc- tion motor drives have high 6 n 1 ; n = odd order harmonic currents, due to absence of back emf for these currents. To sup- press these harmonic currents, either bulky inductive harmonic filters or complex pulse width modulation (PWM) techniques have to be used. This paper proposes a simple harmonic elimination scheme using capacitor fed inverters, for an asymmetrical six- phase induction motor VSI fed drive. Two three phase inverters fed from a single capacitor is used on the open-end side of the motor, to suppress 6 n 1 ; n = odd order harmonics. A PWM scheme that can suppress the harmonics, as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected. The proposed scheme is verified using MATLAB Simulink simulation at different speeds. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. Experimental results are also provided to validate the functionality of the proposed controller
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/42583
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