VALENTE, GIACOMO

VALENTE, GIACOMO  

Dipartimento di Ingegneria e scienze dell'informazione e matematica  

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Titolo Data di pubblicazione Autore(i) File
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs 1-gen-2023 Brilli, Gianluca; Valente, Giacomo; Capotondi, Alessandro; Burgio, Paolo; DI MASCIO, Tania; Valente, Paolo; Marongiu, Andrea
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection 1-gen-2023 Valente, Giacomo; Muttillo, Vittoriano; Federici, Fabio; Pomante, Luigi; Mascio, Tania Di
SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design 1-gen-2023 Pomante, Luigi; Santic, Marco; Muttillo, Vittoriano; Valente, Giacomo
Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project 1-gen-2022 Caruso, Federica; Di Mascio, Tania; Frigioni, Daniele; Pomante, Luigi; Valente, Giacomo; Delucchi, Stefano; Burgio, Paolo; Frangia, Manuel Di; Paganin, Luca; Garibotto, Chiara; Vallocchia, Damiano
MONICA “On-the-Job” Technology-Enhanced Learning Environment: An Empirical Evaluation 1-gen-2022 Caruso, F.; Di Mascio, T.; Peretti, S.; Pomante, L.; Valente, G.
A Composable Monitoring System for Heterogeneous Embedded Platforms 1-gen-2021 Valente, G.; Fanni, T.; Sau, C.; Di Mascio, T.; Pomante, L.; Palumbo, F.
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 1-gen-2021 Sau, C.; Rinaldi, C.; Pomante, L.; Palumbo, F.; Valente, G.; Fanni, T.; Martinez, M.; van der Linden, F.; Basten, T.; Geilen, M.; Peeren, G.; Kadlec, J.; Jääskeläinen, P.; Bulej, L.; Barranco, F.; Saarinen, J.; Säntti, T.; Zedda, M. K.; Sanchez, V.; Nikkhah, S. T.; Goswami, D.; Amat, G.; Maršík, L.; van Helvoort, M.; Medina, L.; Al-Ars, Z.; de Beer, A.
An investigation of dynamic partial reconfiguration offloading in hard real-time systems. 1-gen-2021 D'Andrea, G.; Valente, G.; Pomante, L.; Di Mascio, T.
MONICA vision: An approach, a model and the interactive tools for cyber-physical systems designers 1-gen-2021 Di Mascio, T.; Caruso, F.; Tarantino, L.; Valente, G.
An Intelligent Informative Totem Application Based on Deep CNN in Edge Regime 1-gen-2020 Giammatteo, Paolo; Valente, Giacomo; D'Ortenzio, Alessandro
Dynamic Partial Reconfiguration Profitability for Real-Time Systems 1-gen-2020 Valente, Giacomo; DI MASCIO, Tania; D'Andrea, Gabriella; Pomante, Luigi
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project 1-gen-2020 Pomante, L.; Palumbo, F.; Rinaldi, C.; Valente, G.; Sau, ; C., and Fanni; T., and Linden; F. V. D., and Basten; T., and Geilen; M., and Peeren; G., and Kadlec; J., and Jaaskelainen; P., and Martinez; M., and Saarinen; J., and Santti; T., and Zedda; M. K., and Sanchez; V., and Goswami; D., and Al-Ars; Z., and Beer; A., D.
Layering the monitoring action for improved flexibility and overhead control: work-in-progress 1-gen-2020 Valente, Giacomo; Fanni, Tiziana; Sau, Carlo; DI BATTISTA, Francesco
An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: The 'Design for Monitorability' Project-Work-in-Progress 1-gen-2020 Valente, G.; Di Mascio, T.; Pomante, L.; Stoico, V.
Run-Time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow 1-gen-2020 Muttillo, V; Valente, G.; Pomante, L.; Posadas, H.; Merino, J.; Villar, E.
Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges 1-gen-2020 D'Andrea, Gabriella; Valente, Giacomo
MECO: An Autonomic Manager For Edge-Computing Platforms 1-gen-2019 D'Andrea, Gabriella; DI MASCIO, Tania; Pomante, Luigi; Valente, Giacomo
A lightweight , hardware-based support for isolation in mixed-criticality Network-on-Chip architectures 1-gen-2019 Valente, Giacomo; Giammatteo, Paolo; Muttillo, Vittoriano; Pomante, Luigi; DI MASCIO, Tania
Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable? 1-gen-2019 D'Andrea, G.; Di Mascio, T.; Valente, G.
SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications 1-gen-2019 Valente, Giacomo; Muttillo, Vittoriano; Muttillo, Mirco; Barile, Gianluca; Leoni, Alfiero; Tiberti, Walter; Pomante, Luigi