FORNACIARI, WILLIAM
FORNACIARI, WILLIAM
Affinity-driven system design exploration for heterogeneous multiprocessor SoC
2006-01-01 Brandolese, C.; Fornaciari, William; Pomante, L.; Salice, Fabio; Sciuto, D.
DPM at OS level: low-power scheduling policies
2006-01-01 Brandolese, C; Fornaciari, W; Salice, F; Zafalon, R; Pomante, L
Energy aware scheduling of processes at OS level
2006-01-01 Brandolese, C.; Fornaciari, W.; Salice, F.; Pomante, L.; Zafalon, R.
Partitioning of embedded applications onto heterogeneous multiprocessor architectures
2003-01-01 Salice, F.; Del Vecchio, L.; Pomante, L.; Fornaciari, W.
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System
2003-01-01 Pomante, L; Salice, F; Fornaciari, W; Sciuto, D
SystemC-Plus Complex Data Types for Telecom Applications
2002-01-01 Bombana, M; Pomante, L; Fornaciari, W
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
2002-01-01 Sciuto, D.; Salice, F.; Pomante, L.; Fornaciari, W.
Hardware-Software Timing Simulation Environment for Multiprocessor Embedded Systems
2001-01-01 Fornaciari, W; Pomante, L.; Salice, F.; Sciuto, D.
HW/SW co-simulation for fast design-space exploration of multiprocessor embedded systems
2001-01-01 Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D.
A multi-level strategy for software power estimation
2000-01-01 Brandolese, C.; Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Affinity-driven system design exploration for heterogeneous multiprocessor SoC | 1-gen-2006 | Brandolese, C.; Fornaciari, William; Pomante, L.; Salice, Fabio; Sciuto, D. | |
| DPM at OS level: low-power scheduling policies | 1-gen-2006 | Brandolese, C; Fornaciari, W; Salice, F; Zafalon, R; Pomante, L | |
| Energy aware scheduling of processes at OS level | 1-gen-2006 | Brandolese, C.; Fornaciari, W.; Salice, F.; Pomante, L.; Zafalon, R. | |
| Partitioning of embedded applications onto heterogeneous multiprocessor architectures | 1-gen-2003 | Salice, F.; Del Vecchio, L.; Pomante, L.; Fornaciari, W. | |
| An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System | 1-gen-2003 | Pomante, L; Salice, F; Fornaciari, W; Sciuto, D | |
| SystemC-Plus Complex Data Types for Telecom Applications | 1-gen-2002 | Bombana, M; Pomante, L; Fornaciari, W | |
| Metrics for design space exploration of heterogeneous multiprocessor embedded systems | 1-gen-2002 | Sciuto, D.; Salice, F.; Pomante, L.; Fornaciari, W. | |
| Hardware-Software Timing Simulation Environment for Multiprocessor Embedded Systems | 1-gen-2001 | Fornaciari, W; Pomante, L.; Salice, F.; Sciuto, D. | |
| HW/SW co-simulation for fast design-space exploration of multiprocessor embedded systems | 1-gen-2001 | Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D. | |
| A multi-level strategy for software power estimation | 1-gen-2000 | Brandolese, C.; Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D. |