MUTTILLO, VITTORIANO
MUTTILLO, VITTORIANO
Towards the end of the ECSEL Project “iRel40”: three years of Intelligent Reliability
2026-01-01 Brinkfeldt, K.; Bulut, B.; Caruso, F.; Mascio, T. D.; Fazzini, L.; Frigioni, D.; Moser, J.; Muttillo, V.; Pomante, L.; Pressel, K.; Rzepka, S.; Santic, M.; Soyturk, M.; Valente, G.; Van Driel, W.; Zhao, S.
Empowering Retail Visitors Through Edge AI: A User-Centered Case Study of Cooperative Totem Systems
2026-01-01 Brilli, Gianluca; Caruso, Federica; Valente, Giacomo; Carlevaro, Alberto; Garibotto, Chiara; Motta, Jacopo; Muttillo, Vittoriano; Vallocchia, Damiano; Burgio, Paolo
System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric
2025-01-01 Muttillo, Vittoriano; Stoico, Vincenzo; Valente, Giacomo; Santic, Marco; Pomante, Luigi; Frigioni, Daniele
A New HW/SW Co-Design Approach for Monitored Systems-on-Chip Development
2025-01-01 Valente, Giacomo; Muttillo, Vittoriano; Pomante, Luigi; Frigioni, Daniele; Di Mascio, Tania
Leveraging traffic injection and quality-of-service to control the reconfiguration delay
2025-01-01 Valente, Giacomo; Muttillo, Vittoriano; Federici, Fabio; Pomante, Luigi; Di Mascio, Tania
Leveraging synthetic trace generation of modeling operations for intelligent modeling assistants using large language models
2025-01-01 Muttillo, V.; Di Sipio, C.; Rubei, R.; Berardinelli, L.
SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations
2024-01-01 Muttillo, Vittoriano; Stoico, Vincenzo; Santic, Marco; Valente, Giacomo; Pomante, Luigi; Frigioni, Daniele
Towards Synthetic Trace Generation of Modeling Operations using In-Context Learning Approach
2024-01-01 Muttillo, V.; Di Sipio, C.; Rubei, R.; Berardinelli, L.; Dehghani, M.
SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design
2023-01-01 Pomante, Luigi; Santic, Marco; Muttillo, Vittoriano; Valente, Giacomo
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection
2023-01-01 Valente, Giacomo; Muttillo, Vittoriano; Federici, Fabio; Pomante, Luigi; Di Mascio, Tania
AIDOaRt: AI-augmented Automation for DevOps, a Model-based Framework for Continuous Development in Cyber-Physical Systems
2021-01-01 Eramo, Romina; Muttillo, Vittoriano; Berardinelli, Luca; Brunelière, Hugo; Gómez, Abel; Bagnato, Alessandra; Sadovykh, Andrey; Cicchetti, Antonio
An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems
2020-01-01 Muttillo, V; Giammatteo, P; Fiorilli, G; Pomante, L
Run-Time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow
2020-01-01 Muttillo, V; Valente, G.; Pomante, L.; Posadas, H.; Merino, J.; Villar, E.
A Low Cost and Flexible Power Line Communication Sensory System for Home Automation
2020-01-01 Muttillo, M.; Muttillo, V.; Pomante, L.; Pantoli, L.
SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems
2020-01-01 Pomante, L; Muttillo, V; Santic, M; Serri, P
Hepsycode-MC: Electronic System-Level Methodology For Hw/Sw Co-Design Of Mixed-Criticality Embedded Systems
2019-01-01 Pomante, Luigi; Muttillo, Vittoriano; Santic, Marco; Incerto, Emilio
A lightweight , hardware-based support for isolation in mixed-criticality Network-on-Chip architectures
2019-01-01 Valente, Giacomo; Giammatteo, Paolo; Muttillo, Vittoriano; Pomante, Luigi; Di Mascio, Tania
Benchmarking analysis and characterization of hypervisors for space multicore systems
2019-01-01 Muttillo, V; Tiberi, Luca; Pomante, L; Serri, P
SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications
2019-01-01 Valente, Giacomo; Muttillo, Vittoriano; Muttillo, Mirco; Barile, Gianluca; Leoni, Alfiero; Tiberti, Walter; Pomante, Luigi
HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions
2019-01-01 Muttillo, V; Pomante, L; Balbastre, P; Simo, J; Crespo, A
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Towards the end of the ECSEL Project “iRel40”: three years of Intelligent Reliability | 1-gen-2026 | Brinkfeldt, K.; Bulut, B.; Caruso, F.; Mascio, T. D.; Fazzini, L.; Frigioni, D.; Moser, J.; Muttillo, V.; Pomante, L.; Pressel, K.; Rzepka, S.; Santic, M.; Soyturk, M.; Valente, G.; Van Driel, W.; Zhao, S. | |
| Empowering Retail Visitors Through Edge AI: A User-Centered Case Study of Cooperative Totem Systems | 1-gen-2026 | Brilli, Gianluca; Caruso, Federica; Valente, Giacomo; Carlevaro, Alberto; Garibotto, Chiara; Motta, Jacopo; Muttillo, Vittoriano; Vallocchia, Damiano; Burgio, Paolo | |
| System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric | 1-gen-2025 | Muttillo, Vittoriano; Stoico, Vincenzo; Valente, Giacomo; Santic, Marco; Pomante, Luigi; Frigioni, Daniele | |
| A New HW/SW Co-Design Approach for Monitored Systems-on-Chip Development | 1-gen-2025 | Valente, Giacomo; Muttillo, Vittoriano; Pomante, Luigi; Frigioni, Daniele; Di Mascio, Tania | |
| Leveraging traffic injection and quality-of-service to control the reconfiguration delay | 1-gen-2025 | Valente, Giacomo; Muttillo, Vittoriano; Federici, Fabio; Pomante, Luigi; Di Mascio, Tania | |
| Leveraging synthetic trace generation of modeling operations for intelligent modeling assistants using large language models | 1-gen-2025 | Muttillo, V.; Di Sipio, C.; Rubei, R.; Berardinelli, L. | |
| SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations | 1-gen-2024 | Muttillo, Vittoriano; Stoico, Vincenzo; Santic, Marco; Valente, Giacomo; Pomante, Luigi; Frigioni, Daniele | |
| Towards Synthetic Trace Generation of Modeling Operations using In-Context Learning Approach | 1-gen-2024 | Muttillo, V.; Di Sipio, C.; Rubei, R.; Berardinelli, L.; Dehghani, M. | |
| SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design | 1-gen-2023 | Pomante, Luigi; Santic, Marco; Muttillo, Vittoriano; Valente, Giacomo | |
| Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection | 1-gen-2023 | Valente, Giacomo; Muttillo, Vittoriano; Federici, Fabio; Pomante, Luigi; Di Mascio, Tania | |
| AIDOaRt: AI-augmented Automation for DevOps, a Model-based Framework for Continuous Development in Cyber-Physical Systems | 1-gen-2021 | Eramo, Romina; Muttillo, Vittoriano; Berardinelli, Luca; Brunelière, Hugo; Gómez, Abel; Bagnato, Alessandra; Sadovykh, Andrey; Cicchetti, Antonio | |
| An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems | 1-gen-2020 | Muttillo, V; Giammatteo, P; Fiorilli, G; Pomante, L | |
| Run-Time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow | 1-gen-2020 | Muttillo, V; Valente, G.; Pomante, L.; Posadas, H.; Merino, J.; Villar, E. | |
| A Low Cost and Flexible Power Line Communication Sensory System for Home Automation | 1-gen-2020 | Muttillo, M.; Muttillo, V.; Pomante, L.; Pantoli, L. | |
| SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems | 1-gen-2020 | Pomante, L; Muttillo, V; Santic, M; Serri, P | |
| Hepsycode-MC: Electronic System-Level Methodology For Hw/Sw Co-Design Of Mixed-Criticality Embedded Systems | 1-gen-2019 | Pomante, Luigi; Muttillo, Vittoriano; Santic, Marco; Incerto, Emilio | |
| A lightweight , hardware-based support for isolation in mixed-criticality Network-on-Chip architectures | 1-gen-2019 | Valente, Giacomo; Giammatteo, Paolo; Muttillo, Vittoriano; Pomante, Luigi; Di Mascio, Tania | |
| Benchmarking analysis and characterization of hypervisors for space multicore systems | 1-gen-2019 | Muttillo, V; Tiberi, Luca; Pomante, L; Serri, P | |
| SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications | 1-gen-2019 | Valente, Giacomo; Muttillo, Vittoriano; Muttillo, Mirco; Barile, Gianluca; Leoni, Alfiero; Tiberti, Walter; Pomante, Luigi | |
| HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions | 1-gen-2019 | Muttillo, V; Pomante, L; Balbastre, P; Simo, J; Crespo, A |