MUTTILLO, VITTORIANO
MUTTILLO, VITTORIANO
Dipartimento di Ingegneria e scienze dell'informazione e matematica
System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric
2025-01-01 Muttillo, Vittoriano; Stoico, Vincenzo; Valente, Giacomo; Santic, Marco; Pomante, Luigi; Frigioni, Daniele
SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations
2024-01-01 Muttillo, Vittoriano; Stoico, Vincenzo; Santic, Marco; Valente, Giacomo; Pomante, Luigi; Frigioni, Daniele
SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design
2023-01-01 Pomante, Luigi; Santic, Marco; Muttillo, Vittoriano; Valente, Giacomo
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection
2023-01-01 Valente, Giacomo; Muttillo, Vittoriano; Federici, Fabio; Pomante, Luigi; Mascio, Tania Di
AIDOaRt: AI-augmented Automation for DevOps, a Model-based Framework for Continuous Development in Cyber-Physical Systems
2021-01-01 Eramo, Romina; Muttillo, Vittoriano; Berardinelli, Luca; Brunelière, Hugo; Gómez, Abel; Bagnato, Alessandra; Sadovykh, Andrey; Cicchetti, Antonio
An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems
2020-01-01 Muttillo, V; Giammatteo, P; Fiorilli, G; Pomante, L
SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems
2020-01-01 Pomante, L; Muttillo, V; Santic, M; Serri, P
Run-Time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow
2020-01-01 Muttillo, V; Valente, G.; Pomante, L.; Posadas, H.; Merino, J.; Villar, E.
A Low Cost and Flexible Power Line Communication Sensory System for Home Automation
2020-01-01 Muttillo, M.; Muttillo, V.; Pomante, L.; Pantoli, L.
Hepsycode-MC: Electronic System-Level Methodology For Hw/Sw Co-Design Of Mixed-Criticality Embedded Systems
2019-01-01 Pomante, Luigi; Muttillo, Vittoriano; Santic, Marco; Incerto, Emilio
The AQUAS ECSEL Project Aggregated Quality Assurance for Systems: Co-Engineering Inside and Across the Product Life Cycle
2019-01-01 Pomante, L.; Muttillo, V.; Křena, B.; Vojnar, T.; Veljković, F.; Magnin, P.; Matschnig, M.; Fischer, B.; Martinez, J.; Gruber, T.
Tuning DSE for heterogeneous multi-processor embedded systems by means of a self-equalized weighted sum method
2019-01-01 Muttillo, V.; Fiorilli, G.; Di Mascio, T.
Benchmarking analysis and characterization of hypervisors for space multicore systems
2019-01-01 Muttillo, V; Tiberi, Luca; Pomante, L; Serri, P
SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications
2019-01-01 Valente, Giacomo; Muttillo, Vittoriano; Muttillo, Mirco; Barile, Gianluca; Leoni, Alfiero; Tiberti, Walter; Pomante, Luigi
A lightweight , hardware-based support for isolation in mixed-criticality Network-on-Chip architectures
2019-01-01 Valente, Giacomo; Giammatteo, Paolo; Muttillo, Vittoriano; Pomante, Luigi; DI MASCIO, Tania
HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions
2019-01-01 Muttillo, V; Pomante, L; Balbastre, P; Simo, J; Crespo, A
Criticality-aware design space exploration for mixed-criticality embedded systems
2018-01-01 Pomante, L.; Muttillo, V.; Valente, G.
Design space exploration for mixed-criticality embedded systems considering hypervisor-based SW Partitions
2018-01-01 Muttillo, V.; Valente, G.; Pomante, L.
Criticality-driven design space exploration for mixed-criticality heterogeneous parallel embedded systems
2018-01-01 Muttillo, V.; Valente, G.; Pomante, L.
Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements
2018-01-01 Muttillo, Vittoriano; Valente, Giacomo