SALICE, FABIO

SALICE, FABIO  

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Titolo Data di pubblicazione Autore(i) File
CC4CS: An off-the-shelf unifying statement-level performance metric for HW/SW technologies 1-gen-2018 Muttillo, V.; Stoico, Vincenzo; Valente, G.; CASO D'ANTONIO, Fabio; Pomante, L.; Salice, F.
DPM at OS level: low-power scheduling policies 1-gen-2006 Brandolese, C; Fornaciari, W; Salice, F; Zafalon, R; Pomante, L
Affinity-driven system design exploration for heterogeneous multiprocessor SoC 1-gen-2006 Brandolese, C.; Fornaciari, William; Pomante, L.; Salice, Fabio; Sciuto, D.
Energy aware scheduling of processes at OS level 1-gen-2006 Brandolese, C.; Fornaciari, W.; Salice, F.; Pomante, L.; Zafalon, R.
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System 1-gen-2003 Pomante, L; Salice, F; Fornaciari, W; Sciuto, D
The Design of Reliable Devices for Mission-Critical Applications 1-gen-2003 Bolchini, C.; Pomante, L.; Salice, F.; Sciuto, D.
Partitioning of embedded applications onto heterogeneous multiprocessor architectures 1-gen-2003 Salice, F.; Del Vecchio, L.; Pomante, L.; Fornaciari, W.
Metrics for design space exploration of heterogeneous multiprocessor embedded systems 1-gen-2002 Sciuto, D.; Salice, F.; Pomante, L.; Fornaciari, W.
Hardware-Software Timing Simulation Environment for Multiprocessor Embedded Systems 1-gen-2001 Fornaciari, W; Pomante, L.; Salice, F.; Sciuto, D.
On-line fault detection in a hardware/software co-design environment: System partitioning 1-gen-2001 Bolchini, C.; Pomante, L.; Salice, F.; Sciuto, D.
HW/SW co-simulation for fast design-space exploration of multiprocessor embedded systems 1-gen-2001 Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D.
A multi-level strategy for software power estimation 1-gen-2000 Brandolese, C.; Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D.
Synthesis methodology aimed at improving the quality of TSC devices 1-gen-1999 Bolchini, C.; Pomante, L.; Salice, F.; Sciuto, D.