SALICE, FABIO
SALICE, FABIO
CC4CS: An off-the-shelf unifying statement-level performance metric for HW/SW technologies
2018-01-01 Muttillo, V.; Stoico, Vincenzo; Valente, G.; CASO D'ANTONIO, Fabio; Pomante, L.; Salice, F.
DPM at OS level: low-power scheduling policies
2006-01-01 Brandolese, C; Fornaciari, W; Salice, F; Zafalon, R; Pomante, L
Affinity-driven system design exploration for heterogeneous multiprocessor SoC
2006-01-01 Brandolese, C.; Fornaciari, William; Pomante, L.; Salice, Fabio; Sciuto, D.
Energy aware scheduling of processes at OS level
2006-01-01 Brandolese, C.; Fornaciari, W.; Salice, F.; Pomante, L.; Zafalon, R.
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System
2003-01-01 Pomante, L; Salice, F; Fornaciari, W; Sciuto, D
The Design of Reliable Devices for Mission-Critical Applications
2003-01-01 Bolchini, C.; Pomante, L.; Salice, F.; Sciuto, D.
Partitioning of embedded applications onto heterogeneous multiprocessor architectures
2003-01-01 Salice, F.; Del Vecchio, L.; Pomante, L.; Fornaciari, W.
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
2002-01-01 Sciuto, D.; Salice, F.; Pomante, L.; Fornaciari, W.
Hardware-Software Timing Simulation Environment for Multiprocessor Embedded Systems
2001-01-01 Fornaciari, W; Pomante, L.; Salice, F.; Sciuto, D.
On-line fault detection in a hardware/software co-design environment: System partitioning
2001-01-01 Bolchini, C.; Pomante, L.; Salice, F.; Sciuto, D.
HW/SW co-simulation for fast design-space exploration of multiprocessor embedded systems
2001-01-01 Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D.
A multi-level strategy for software power estimation
2000-01-01 Brandolese, C.; Fornaciari, W.; Pomante, L.; Salice, F.; Sciuto, D.
Synthesis methodology aimed at improving the quality of TSC devices
1999-01-01 Bolchini, C.; Pomante, L.; Salice, F.; Sciuto, D.