In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits.

Impact of Voltage Bias on through silicon Vias (TSV) Depletion and Crosstalk

Piersanti, Stefano;de Paulis, Francesco;Orlandi, Antonio;
2016-01-01

Abstract

In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits.
978-150900349-5
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/100124
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