IRIS

PIERSANTI, STEFANO

PIERSANTI, STEFANO  

Dipartimento di Ingegneria industriale e dell'informazione e di economia  

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Risultati 1 - 18 di 18 (tempo di esecuzione: 0.042 secondi).
Titolo Data di pubblicazione Autore(i) File
Decoupling capacitors placement at board level adopting a nature-inspired algorithm 1-gen-2019 Piersanti, S.; Cecchetti, R.; Olivieri, C.; de Paulis, F.; Orlandi, A.; Buecker, M.
Reduction of IC Heatsink Radiation by Optimization of Absorbing Material Geometry 1-gen-2019 De Paulis, F.; Piersanti, S.; Orlandi, A.; Connor, S.; Dixon, P.
Efficient iterative process based on an improved genetic algorithm for decoupling capacitor placement at board level 1-gen-2019 de Paulis, F.; Cecchetti, R.; Olivieri, C.; Piersanti, S.; Orlandi, A.; Buecker, M.
Decoupling Capacitors Placement for a Multichip PDN by a Nature-Inspired Algorithm 1-gen-2018 Piersanti, Stefano; De Paulis, Francesco; Olivieri, Carlo; Orlandi, Antonio
Impact of chip and interposer PDN to eye diagram in high speed channels 1-gen-2018 De Paulis, Francesco; Zhao, Biyao; Piersanti, Stefano; Cho, Jonghyun; Cecchetti, Riccardo; Achkir, Brice; Orlandi, Antonio; Fan, Jun
Through-silicon via capacitance-voltage hysteresis modeling for 2.5-D and 3-D IC 1-gen-2017 Kim, Dong-Hyun; Kim, Youngwoo; Cho, Jonghyun; Bae, Bumhee; Park, Junyong; Lee, Hyunsuk; Lim, Jaemin; Kim, Jonghoon J.; Piersanti, Stefano; DE PAULIS, Francesco; Orlandi, Antonio; Kim, Joungho
TEM-Like Launch Geometries and Simplified De-Embedding for Accurate Through Silicon Via (TSV) Measurement Characterization 1-gen-2017 DE PAULIS, Francesco; Piersanti, Stefano; Orlandi, Antonio; Wang, Qian; Cho, Jonghyun; Erickson, Nicholas; Achkir, Bricge; Fan, Jun; Drewniak, James
Algorithm for Extracting Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling and Robustness Analysis 1-gen-2017 Piersanti, Stefano; Pellegrino, Enza; DE PAULIS, Francesco; Orlandi, Antonio; Jung, Daniel H.; Kim, Dong-Hyun; Kim, Joungho; Fan, Jun
Detection of Open and Short Faults in 3D-ICs based on Through Silicon Via (TSV) 1-gen-2017 Piersanti, Stefano; DE PAULIS, Francesco; Orlandi, Antonio; Jung, Daniel H.; Kim, Joungho; Fan, Jun
Novel De-embedding Metrology and Broadband Microprobe Measurement for Through-Silicon Via Pair in Silicon Interposer 1-gen-2017 Wang, Qian; Cho, Jonghyun; Erickson, Nicholas; Hwang, Chulsoon; DE PAULIS, Francesco; Piersanti, Stefano; Orlandi, Antonio; Achkir, Brice; Fan, Jun
Near Field Shielding Performances of EMI Noise Suppression Absorbers 1-gen-2017 Piersanti, Stefano; DE PAULIS, Francesco; Orlandi, Antonio; Connor, Sam; Liu, Qian; Archambeault, Bruce; Dixon, Paul; Ali Khorrami, Mohammad; Drewniak, James
Electrical Performance Analysis and Modeling Optimization of Test Patterns Used in De-embedding Method for Through Silicon Via (TSV) Pair in Silicon Interposer 1-gen-2016 Q. Wang, N. Erickson; Cho, J.; Hwang, C.; Paulis, Francesco de; Piersanti, Stefano; Achkir, B.; Orlandi, Antonio
Identification of Jiles-Atherton Model Parameters for Circuit Application by non linear optimization methods 1-gen-2016 Piersanti, Stefano; Pellegrino, Enza; Tresca, G.; Paulis, Francesco De; Orlandi, Antonio
Impact of Voltage Bias on through silicon Vias (TSV) Depletion and Crosstalk 1-gen-2016 Piersanti, Stefano; de Paulis, Francesco; Orlandi, Antonio; Fan, Jun; Archir, Brice
Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling 1-gen-2016 Piersanti, Stefano; Pellegrino, Enza; de Paulis, Francesco; Orlandi, Antonio; Kim, J.; Fan, J.
Modeling optimization of test patterns used in de-embedding method for through silicon via (TSV) measurement in silicon interposer 1-gen-2016 Wang, Q.; Erickson, N.; Cho, J.; Hwang, C.; Fan, J.; De Paulis, F.; Piersanti, S.; Orlandi, A.; Achkir, B.
Through Silicon Via Time Domain Crosstalk Modeling Considering Hysteretic Coupling Capacitance 1-gen-2015 Piersanti, Stefano; de Paulis, Francesco; Orlandi, Antonio; Kim, D. H.; Cho, J.; Kim, J.
Equivalent Circuit Modeling of Dielectric Hysteresis Loops in Through Silicon Vias 1-gen-2015 Piersanti, S.; De Paulis, F.; Orlandi, A.; Kim, D. H.; Kim, D. H.; Kim, J.; Fan, J.