In this paper, the electrical performance of the test patterns used in the de-embedding method for TSV characterization was studied thoroughly. For all test patterns, full wave models were built and then analyzed based on simulated electrical performances. Equivalent circuit model analysis and parametric study results of the test patterns further demonstrate the accuracy of the full wave models. Furthermore, Scanning Electron Microscopy (SEM) measurements were taken for all the test patterns, and full wave models were optimized based on the measured dimensions. Finally, the response of the TSV pair was obtained by de-embedding the pads and traces from the TSV pair simulation with the test fixtures. Good agreement between the de-embedded results with analytical characterization and the full-wave simulation for a single TSV pair was achieved.

Modeling optimization of test patterns used in de-embedding method for through silicon via (TSV) measurement in silicon interposer

De Paulis F.;Piersanti S.;Orlandi A.;
2016-01-01

Abstract

In this paper, the electrical performance of the test patterns used in the de-embedding method for TSV characterization was studied thoroughly. For all test patterns, full wave models were built and then analyzed based on simulated electrical performances. Equivalent circuit model analysis and parametric study results of the test patterns further demonstrate the accuracy of the full wave models. Furthermore, Scanning Electron Microscopy (SEM) measurements were taken for all the test patterns, and full wave models were optimized based on the measured dimensions. Finally, the response of the TSV pair was obtained by de-embedding the pads and traces from the TSV pair simulation with the test fixtures. Good agreement between the de-embedded results with analytical characterization and the full-wave simulation for a single TSV pair was achieved.
978-1-5090-1442-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11697/145267
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