Progettazione e Implementazione su FPGA Riconfigurabile di Processori Digitali Trasparenti Satellitari

In the context of satellite communications, a key role is played by the on-board processor. In particular, the development of satellite transponders have evolved from the analog bent-pipe transponders to the digital regenerative ones. Recently, a new generation of transponders, namely semi-transparent transponders, have been emerging. The core components of these transponders are i) a digital transparent section, namely Digital Transparent Processor (DTP), which is devoted to the routing of the traffic data, and ii) a regenerative section that is devoted to the media access control. In this way, the dynamic reconfiguration of connectivity plans and the adaptation to evolving communications standards, are achieved by the semi-transparent transponder. Regarding the DTP, this section can efficiently decouple the on-board design from the physical layer communications standard. In the above context, a great relevance is taken by the need to define design criteria of the transparent digital section that take into account the complexity of the hardware and the link-budget constraints. In this perspective, an equivalent noise model has been recently defined by our research group in order to characterize the non-ideal behavior of the on-board processor. The model relies on an extended notion of noise figure that allows a radio link-budget to natively incorporate the non-ideal behavior (e.g., quantization and rounding errors and linear distortions) of the various DTP segments. In this thesis work the following research advances are provided: 1) an explicit computation of the implementation complexity of a DTP and 2) a methodology to carry out a complete design flow that moves from system requirements and brings to a detailed definition of digital hardware (HW) components in the DTP. Through numerical examples we demonstrate that, given a requirement on the overall link-budget performance in contexts of practical interest, significant differences in HW complexity are obtained for different design choices. Moreover, having also completed a full FPGA implementation of a whole DTP chain, a further extension of the modelling approach in order to incorporate power consumption of HW architectures is presented. Results are provided as obtained for different configurations, requirements and design objectives.