SAIF, AHMED MAJED AHMED
SAIF, AHMED MAJED AHMED
Dipartimento di Ingegneria e scienze dell'informazione e matematica
Progettazione e implementazione del controllo di SSBC convertitore multilivello per compensatore sincrono statico
2021-05-03 Saif, AHMED MAJED AHMED
Power Quality Improvement for Chopper-Cell Based Modular Multilevel Converters
2019-01-01 Saif, A. M.; Buccella, C.; Cimoroni, M. G.; Cecati, C.
On Control Design and Implementation of Multilevel SSBC STATCOM Using FPGA
2019-01-01 Saif, AHMED MAJED AHMED; Cecati, Carlo; De Paulis, Elena; Buccella, Concettina
Design and cost analysis for STATCOM in low and medium voltage systems
2018-01-01 Saif, AHMED MAJED AHMED; Buccella, Concettina; Patel, VIDHI MANILAL; Tinari, Mario; Cecati, Carlo
Performance Comparison of Multilevel Inverters for E-transportation
2018-01-01 Patel, Vidhi; Buccella, Concettina; Saif, Ahmed Majed; Tinari, Mario; Cecati, Carlo
Harmonic elimination procedure for cascaded multilevel inverters having a particular even number of dc sources
2018-01-01 Buccella, C.; Cimoroni, M. G.; Patel, V.; Saif, A. M.; Tinari, M.; Cecati, C.; Babaei, E.
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
Progettazione e implementazione del controllo di SSBC convertitore multilivello per compensatore sincrono statico | 3-mag-2021 | Saif, AHMED MAJED AHMED | |
Power Quality Improvement for Chopper-Cell Based Modular Multilevel Converters | 1-gen-2019 | Saif, A. M.; Buccella, C.; Cimoroni, M. G.; Cecati, C. | |
On Control Design and Implementation of Multilevel SSBC STATCOM Using FPGA | 1-gen-2019 | Saif, AHMED MAJED AHMED; Cecati, Carlo; De Paulis, Elena; Buccella, Concettina | |
Design and cost analysis for STATCOM in low and medium voltage systems | 1-gen-2018 | Saif, AHMED MAJED AHMED; Buccella, Concettina; Patel, VIDHI MANILAL; Tinari, Mario; Cecati, Carlo | |
Performance Comparison of Multilevel Inverters for E-transportation | 1-gen-2018 | Patel, Vidhi; Buccella, Concettina; Saif, Ahmed Majed; Tinari, Mario; Cecati, Carlo | |
Harmonic elimination procedure for cascaded multilevel inverters having a particular even number of dc sources | 1-gen-2018 | Buccella, C.; Cimoroni, M. G.; Patel, V.; Saif, A. M.; Tinari, M.; Cecati, C.; Babaei, E. |