IRIS
PIERSANTI, STEFANO
 Distribuzione geografica
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Continente #
NA - Nord America 549
EU - Europa 343
AS - Asia 154
OC - Oceania 4
Continente sconosciuto - Info sul continente non disponibili 2
SA - Sud America 1
Totale 1.053
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Nazione #
US - Stati Uniti d'America 547
IE - Irlanda 156
CN - Cina 92
TR - Turchia 54
IT - Italia 46
DE - Germania 39
UA - Ucraina 33
SE - Svezia 31
GB - Regno Unito 19
FR - Francia 7
FI - Finlandia 6
AU - Australia 4
KR - Corea 4
BE - Belgio 2
CA - Canada 2
SG - Singapore 2
A2 - ???statistics.table.value.countryCode.A2??? 1
CH - Svizzera 1
CL - Cile 1
EU - Europa 1
IN - India 1
NL - Olanda 1
RS - Serbia 1
RU - Federazione Russa 1
TW - Taiwan 1
Totale 1.053
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Città #
Dublin 156
Chandler 138
Jacksonville 132
Izmir 39
Nanjing 28
Lawrence 19
New York 18
Princeton 18
Boardman 16
L'aquila 16
Ashburn 15
Wilmington 15
Ann Arbor 12
San Mateo 12
Nanchang 10
Milan 8
Shenyang 8
Beijing 7
Rome 7
Woodbridge 7
Seattle 6
Tianjin 6
Changsha 5
Berlin 4
Jinan 4
Rolla 4
Zhengzhou 4
Cervaro 3
Dearborn 3
Guangzhou 3
Harbin 3
Kitzingen 3
Kunming 3
Verona 3
Washington 3
Brussels 2
Houston 2
Lanzhou 2
Melbourne 2
Montesilvano Marina 2
Norwalk 2
San Francisco 2
San Jose 2
Shanghai 2
Toronto 2
Vasto 2
Arezzo 1
Belgrade 1
Brisbane 1
Cairo Montenotte 1
Canberra 1
Chicago 1
Fremont 1
Grafing 1
Hebei 1
Hefei 1
Jiaxing 1
Krasnoyarsk 1
Luleå 1
Mountain View 1
Phoenix 1
Redwood City 1
Singapore 1
Taipei 1
Taizhou 1
Totale 779
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Nome #
Algorithm for Extracting Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling and Robustness Analysis 111
Equivalent Circuit Modeling of Dielectric Hysteresis Loops in Through Silicon Vias 85
Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling 77
Decoupling Capacitors Placement for a Multichip PDN by a Nature-Inspired Algorithm 73
Electrical Performance Analysis and Modeling Optimization of Test Patterns Used in De-embedding Method for Through Silicon Via (TSV) Pair in Silicon Interposer 70
Identification of Jiles-Atherton Model Parameters for Circuit Application by non linear optimization methods 70
TEM-Like Launch Geometries and Simplified De-Embedding for Accurate Through Silicon Via (TSV) Measurement Characterization 66
Novel De-embedding Metrology and Broadband Microprobe Measurement for Through-Silicon Via Pair in Silicon Interposer 66
Detection of Open and Short Faults in 3D-ICs based on Through Silicon Via (TSV) 62
Through-silicon via capacitance-voltage hysteresis modeling for 2.5-D and 3-D IC 62
Through Silicon Via Time Domain Crosstalk Modeling Considering Hysteretic Coupling Capacitance 53
Near Field Shielding Performances of EMI Noise Suppression Absorbers 53
Impact of Voltage Bias on through silicon Vias (TSV) Depletion and Crosstalk 52
Impact of chip and interposer PDN to eye diagram in high speed channels 49
Efficient iterative process based on an improved genetic algorithm for decoupling capacitor placement at board level 45
Decoupling capacitors placement at board level adopting a nature-inspired algorithm 40
Modeling optimization of test patterns used in de-embedding method for through silicon via (TSV) measurement in silicon interposer 32
Reduction of IC Heatsink Radiation by Optimization of Absorbing Material Geometry 23
Totale 1.089
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Categoria #
all - tutte 4.069
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 4.069
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/201957 0 0 0 0 0 0 0 0 0 0 0 57
2019/2020143 23 0 17 0 0 17 31 1 16 16 2 20
2020/2021137 1 18 1 18 19 5 22 1 18 3 29 2
2021/202294 3 1 14 3 6 0 6 3 5 2 12 39
2022/2023396 21 31 3 33 38 33 2 30 189 1 6 9
2023/202487 15 5 3 3 7 37 0 2 3 1 1 10
Totale 1.089